+92(0) 459-236995 Ext. 123

Biography

Dr. Ateeq Ur Rehman completed his PhD in 2017 from Universiti Teknologi PETRONAS (UTP), Malaysia in Electrical and Electronics Engineering. His focus of research work was “Study on Delay Design for Testability for Functional RTL Circuits”. Prior to this, he completed his B.Sc. Electrical Engineering from N.W.F.P University of Engineering & Tecnology, Peshawar in 2007 followed by MS in Computer Engineering from Lahore University of Management Sciences (LUMS) in 2011. Apart from his association with academic and corporate sectors for his professional interests, Dr. Ateeq has been an active researcher in the fields of VLSI Design, Design-for-Testability (DFT), Digital System Design, System-on-Chip (SoC), Network-on-Chip (NoC), Embedded System and Computer Architecture.

Professional Experience
October 2011 – January 2017 Researcher
Project: Designing a Delay Design-for-Testability for Functional RTL Circuits
Department of Electrical & Electronic Engineering
Universiti Teknologi PETRNOAS (UTP), Malaysia
June 2011 – October 2011 Lecturer
Department of Electrical Engineering,
Government College University (GCU), Pakistan
May 2011 – June 2011 Research Assistant
Project: Developing a labeled corpus for SMS Analytic
Department of Computer Science,
Lahore University of Management Sciences (LUMS), Lahore, Pakistan
June 2010 – August 2010 Research Assistant
Project: Study and propose improvement on Power and efficiency for the SRAM cell
School of Science and Engineering (SSE),
Lahore University of Management Sciences (LUMS), Lahore, Pakistan
Fall 2010 Teaching Assistant
School of Science and Engineering (SSE),
Lahore University of Management Sciences (LUMS), Lahore, Pakistan
February 2009 – July 2009 Preventive Maintenance Engineer
Project: Base transmission systems (BTS) preventive maintenance (MOBILINK Telecom)
MULTI-TECH Systems (Pvt) Ltd., Pakistan
May 2008 – October 2008 Trainee Engineer
Zhongxing Telecom (ZTE), Pakistan
August 2006 Trainee Engineer
National Telecommunication Corporation (NTC), Pakistan
Education Summary
2011 – 2017 Universiti Teknologi PETRNOAS (UTP), Malaysia
Ph.D (Electrical and Electronics Engineering)
Thesis Title: Study on Delay Design-for-Testability for Functional RTL Circuits
Advisors: Dr. Fawnizu Azmadi B Hussin and Dr. Nor Hisham B Hamid
2009 – 2011 Lahore University of Management Sciences (LUMS), Lahore, Pakistan
M.S. (Computer Engineering)
Major Subjects: Digital System Design, VLSI Design, Computer Architecture
2003 – 2007 N.W.F.P University of Engineering and Technology, Peshawar, Pakistan
B.Sc (Electrical Engineering)
Major: Communication/Electronics
Journal Publications
  • Shaheen, A., Hussin, F., Hamid, N., Zain Ali, N., “A Review on Structural Software Based Self-Testing of Embedded Processors”. International Review on Computers and Software (IRECOS), 2014, 9(5), pp. 832-846. (Scopus IF=0.229)
  • A.-U.-R. Shaheen, F. A. Hussin, and N. H. Hamid, “A Hybrid Delay Design for Testability for Nonseparable RTL Controller-Data path Circuits”. Journal of Circuits, Systems and Computers, 26(2):1750021, 2017. (IF= 0.308)
Conference Publications
  • A. U. R. Shaheen, F. A. Hussin, N. H. Hamid and N. B. Z. Ali, “Automatic generation of test instructions for structural faults in processor cores using satisfiability,” SoC Design Conference (ISOCC), 2013 International, Busan, 2013, pp. 388-391. (Scopus indexed)
  • A. U. R. Shaheen, F. A. Hussin, N. H. Hamid and N. B. Z. Ali, “Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram,” Intelligent and Advanced Systems (ICIAS), 2014 5th International Conference on, Kuala Lumpur, 2014, pp. 1-5. (ISI/Scopus indexed)
  • A. U. R. Shaheen, F. A. Hussin and N. H. Hamid, “Delay design for testability for functional RTL circuits,” 2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), Chiang Mai, 2015, pp. 494-499. (Scopus indexed)
  • A. U. R. Shaheen, F. A. Hussin and N. H. Hamid, “False path identification algorithm framework for nonseparable controller-data path circuits,” 2016 6th International Conference on Intelligent and Advanced Systems (ICIAS), Kuala Lumpur, Malaysia, 2016, pp. 1-6. (ISI/Scopus indexed)
Universiti Teknologi PETRONAS (UTP), Malaysia
  • Digital System Design
  • Advance Digital System Design
  • Digital Electronics-II
  • Physics-I
  • Digital Signal Processing
  • Data and Computer Networks
Government College University (GCU), Pakistan
  • Digital System Design
  • Mobile Networks and Data Networks
  • Electromagnetic Theory
Lahore University of Management Sciences (LUMS), Pakistan
  • Digital System Design
Namal College, Mianwali
  • Applied Thermodynamics
  • Digital Logic Design